Referring to FIG. 1, a power semiconductor device according to the prior art includes a semiconductor body having an active region 12 and a termination region 14.
Active region 12 preferably includes the active cells of a power semiconductor device, such as a power MOSFET, which may include at least one PN junction. The PN junction, for example, is a portion of semiconductor body 10 (e.g. epitaxially grown silicon) that includes a base region 16 formed therein. Base region 16 is, as is well known, a diffused region of a conductivity opposite to that of semiconductor body 10. Thus, base region 16 may be P-type when semiconductor body is N-type and vice versa.
Termination region 14 surrounds active region 12, and includes field oxide body 18 formed on semiconductor body 10, first polysilicon field plate 20, oxide body 22, first metallic field plate 24 formed on oxide body 22 and extending therethrough to make electrical contact with first polysilicon field plate 20, second polysilicon field plate 26 formed over field oxide 18 and laterally spaced from first polysilicon field plate 20, second metallic field plate 28 laterally spaced from first metallic field plate 24 formed on oxide body 22 and extending therethrough to make electrical contact with second polysilicon field plate 26 formed over field oxide 18, and third metallic field plate 30 (which is preferably an extension of a power contact, e.g. source contact) disposed partially on oxide body 22, and partially on semiconductor body 10, i.e. making contact with semiconductor body 10.
Termination region 14 further includes a plurality of guard rings 32, 32′, 32″ formed in semiconductor body 16. Each guard ring 32, 32′, 32″ is a diffusion of a conductivity opposite to that of semiconductor body 10 as is conventionally known. Note that at least one guard ring 32 is disposed beneath first polysilicon field plate 20 under a recess 34 in field oxide 18 which is filled with polysilicon from first polysilicon field plate 20. Furthermore, a number of guard rings 32″ are formed beneath respective recesses 34 in field oxide 18, which are filled with polysilicon from second polysilicon field plate 26. In addition, at least one guard ring 32′ is disposed between guard ring 32 and guard rings 32″ laterally beyond the inner boundary (boundary closest to active region 12) of first polysilicon field plate 20 and laterally before the outer boundary (boundary farthest from active region 12) of second polysilicon field plate 26.
The device illustrated in FIG. 1 includes a polysilicon equipotential ring 36 extending from over an edge of field oxide 18 to semiconductor body 10. Also, a diffusion 38 of a conductivity opposite to that of semiconductor body 10 is formed in semiconductor body 10 near the inner boundary of termination region 14.
FIG. 2 illustrates another power semiconductor device according to the prior art which includes a differently-shaped polysilicon equipotential ring 36.
Note that some typical dimensions are shown in the Figs. Table 1 below discloses further typical dimensions for the prior art devices shown by FIGS. 1 and 2.
TABLE 1ABCDFIG. 125 μm5 μm19.6 μm20.6 μmFIG. 225 μm8 μm19.6 μm20.6 μm
A=Spacing from ring 36 to polysilicon field plate 20
B=Width of ring 36 on oxide 18
C=Spacing between inner edge of metallic field plate 24 to guard ring 32
D=Spacing between inner edge of polysilicon field plate 20 to guard ring 32.
The prior art devices illustrated by FIGS. 1 and 2 have exhibited high failure rates. It is desirable to improve the prior art devices.